1. Field of the Invention
The present invention relates to a semiconductor circuit device in which a number of MIS transistors are integrated, and a method for designing the semiconductor circuit device.
2. Description of the Related Art
In recent years, for example, in the field of LSIs, such as MIS semiconductor integrated circuits and the like, design specifications required for integrated circuits have become more diverse and complex with an increase in the fineness of a semiconductor element pattern, a packaging density, and the speed of an operation of semiconductor elements. In general, LSIs (Large Scale Integration) represented by microprocessors are each composed of a number of basic functional unit circuits called cells. In the cell, a number of elements, such as a MIS transistor, a capacitance, a resistance, and the like, are arranged. As the performance and packaging density of LSIs are increased, a circuit design of a cell for determining the performance of the LSI is becoming more important. CAD (Computer Aided Design) tools play a considerably important role in designing the cell circuit with high accuracy.
A circuit simulator is one of the CAD tools which are deeply involved with design accuracy. The circuit simulator performs circuit simulation with respect to a designed cell or LSI, assuming a circuit operation of a cell or an LSI which would be fabricated by the design, based on a net list including information about connection of elements (a transistor, a capacitance, a resistance, etc.), and information about properties of the elements (a transistor size, a capacitance value, a resistance value, etc.). For example, the net list can be extracted from the mask layout of a designed cell using an extraction device for circuits. Also, regarding information about characteristics of transistors, a number of electrical characteristic formulas (hereinafter referred to as transistor models) have been developed so as to reproduce complicated electrical characteristics of transistors on a circuit simulator with high accuracy. Also, in order to reproduce desired transistor characteristics using a transistor model, model parameters included in the transistor model need to be optimized, depending on the desired transistor characteristic (hereinafter referred to as “extraction of model parameters”).
Hereinafter, a cell layout of a conventional semiconductor circuit device, and a transistor model used in design of a conventional cell will be described.
FIG. 10 is a diagram schematically illustrating a structure of an MIS transistor for describing the conventional transistor model. As illustrated in FIG. 10, the transistor model includes an active region Rt surrounded by an isolation region Ris, a gate electrode 1412 extending across the active region Rt into the isolation region Ris on both sides of the active region Rt, a source region 1414a and a drain region 1414b formed in regions located on both sides of the gate electrode 1412 of the active region Rt, and a channel region 1413 formed in a region located under the gate electrode 1412 of the active region Rt. As hatched with slanting lines in FIG. 10, the channel region 1413 of the MIS transistor is defined as an overlapping region between the active region Rt and the gate electrode 1412 in the transistor model. Also, in the transistor model, the current performance of the MIS transistor is determined based on a width W (channel width) and a length L (channel length) of the channel region 1413, an electrical resistance of the active region Rt, and a resistance (not shown) added to the active region Rt, and information about a layout around the transistor is not taken into consideration.
Next, a cell layout will be described with reference to FIG. 11. FIG. 11 illustrates an exemplary cell layout.
FIG. 11 is a plan view schematically illustrating an exemplary layout of a conventional cell 1100 provided in a portion of a semiconductor substrate. In the semiconductor substrate, an N well 1112 and a P well 1113 are provided, and are adjacent to each other via a well boundary 1101. In the N well 1112, a PMIS active region 1104 surrounded by an isolation region Ris is provided. The P well 1113 is provided with an NMIS active region 1105 surrounded by the isolation region Ris. In FIG. 11, one active region is provided in each of the N well 1112 and the P well 1113 as an example, though a considerably large number of active regions are provided in actual semiconductor circuit devices.
A gate 1108 of a P-type MIS transistor is provided on the PMIS active region 1104. A gate 1109 of an N-type MIS transistor is provided on the NMIS active region 1105. Note that, as is similar to well-known MIS transistors, each gate has a so-called insulating gate structure composed of a gate insulating film and a gate electrode, though not illustrated.
Regions located on sides of a gate in each active region are source and drain regions. When a voltage is applied between the source and drain regions, and a bias is applied to the gate, a channel region is formed in a region under the gate of each active region, and a current flows through the channel region.
In the cell 1100 of FIG. 11, a gap between an end in a gate width direction of the N well 1112 (hereinafter denoted as an “N well end 1101′”) and a center line of a contact N-type region 1106 is represented by SP14, a gap between the center line of the contact N-type region 1106 and the PMIS active region 1104 is represented by SP03, a width of the PMIS active region 1104 is represented by SP02, a gap between the PMIS active region 1104 and the well boundary 1101 (i.e., the boundary between the N well 1112 and the P well 1113) is represented by SP01. Also, a gap between an end in a gate width direction of the P well 1113 (hereinafter denoted as a well end 1111′”) and a center line of a contact P-type region 1107 is represented by SN14, a gap between the center line of the contact P-type region 1107 and the NMIS active region 1105 is represented by SN03, a width of the NMIS active region 1105 is represented by SN02, and a gap between the NMIS active region 1105 and the well boundary 1101 is represented by SN01. A cell region 1102 for the P-type MIS transistor is hatched with right-slanting lines having large widths (SP01+SP02+SP03), and a cell region 1103 for the N-type MIS transistor is hatched with left-slanting lines having large widths (SN01+SN02+SN03). Regions on sides of the gate 1108 of the PMIS active region 1104 and the contact P-type region 1107 include a P-type impurity, and regions on sides of the gate 1109 of the NMIS active region 1105 and the contact N-type region 1106 include an N-type impurity.
FIGS. 1A and 1B are diagrams schematically illustrating a step of performing ion implantation using a resist as a mask when a MIS transistor is fabricated. In this step, in order to selectively perform required implantation, a portion into which ions are not to be implanted is covered with a resist film so that impurity ions are implanted into only a required portion. In FIGS. 1A and 1B, since ion implantation is performed with respect to only a PMIS region, a resist is formed on an NMIS region before ion implantation is performed. Typically, as illustrated in FIG. 1A, ideally, a predetermined amount of impurity ions are implanted into a portion which is not covered with the resist. In fact, however, as illustrated in FIG. 1B, impurity ions implanted into the resist are scattered by polymers included in the resist, so that the direction of the implantation is changed (resist scatter), or when the implantation angle is not 0 degrees, or even when the implantation angle is 0 degrees, there are probabilistically ions having an angle which is not 0 degrees, such ions strike a side wall of the resist, so that ions are reflected at some constant rate (resist reflection). These phenomena lead to an effective increase in dose, so that driving force is reduced due to an increase in threshold voltage.
FIG. 2 is a diagram illustrating a change in transistor characteristics when a value of SP01+SP02 is changed in the CMOS transistor of FIG. 11. The vertical axis represents ΔVth which is a difference between a threshold value of a subject transistor and a threshold value of an N-type MIS transistor or a P-type MIS transistor provided alone. Here, a result of simulation with respect to the P-type MIS transistor is shown. In the P-type MIS transistor, it is assumed that a resist is not formed on the N well end 1101′ side (a resist is formed on the well boundary 1101 side). The gate width of the P-type MIS transistor is assumed to be constant.
As can be seen from the result of FIG. 2, in the CMOS transistor, when a transistor is provided at a location close to the well boundary 1101, the threshold value voltage increases. In FIG. 2, it may be considered that a P-type MIS transistor formed alone corresponds to a point of SP01+SP02=1 μm.
In summary, as can be seen from the result of the simulation conducted by the present inventors, the performance of semiconductor circuit devices including a recent miniaturized MIS transistor varies, depending on how much the MIS transistor is distant from the well boundary as well as the gate length and the gate width of the MIS transistor. What has been described above is also described in “Lateral Ion Implant Straggle and Mask Proximity Effect”, IEEE Transaction on Electron Devices, Vol. 50, No. 9, September 2003.
Semiconductor circuit devices can be designed using a method described in “Accounting for Manufacturing Variation with Silicon Modeling”, SoC/SiP Developer's Conference, May 5, 2005 described below.
Note that FIG. 12 is a plan view illustrating a semiconductor circuit device in which cells designed by the conventional method are arranged in an array. In this semiconductor circuit device, N wells 1212 and P wells 1213 are alternately arranged in a length direction (gate width direction). A cell region 1202 for a P-type MIS transistor and a cell region 1203 for an N-type MIS transistor correspond to the cell region 1102 for a P-type MIS transistor and the cell region 1103 for an N-type MIS transistor of FIG. 11. The N well 1212 and the P well 1213 correspond to the N well 1112 and the P well 1113 of FIG. 11. A well boundary 1201 which is a boundary between the N well 1212 and the P well 1213 corresponds to the well boundary 1101 of FIG. 11. An N well end 1201′ corresponds to the N well end 1101′ of FIG. 11.